University of Kurdistan logoNanoelectronics: A New Perspective on TransportWeek 6 · The nanotransistor · C3
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WEEK 6 · THE NANOTRANSISTOR · C3

Nanoelectronics:
A New Perspective on Transport

Gate control, current saturation, charging and quantum capacitance
Prof. Mohammad RazaghiUniversity of Kurdistan · Graduate course in Electronics Engineering
Based on S. Datta, Lessons from Nanoelectronics, Part A: Basic Concepts, Chapter 7
Part 1 is the fixed lecture (Ch. 7). Part 2, after the divider, is circular session C3 on Weeks 5–6.

RecapWhere we are

Week 5 gave us

  • D(E) and M(E) from counting states
  • 2D band: D constant, M ∝ √(E − Ec)
  • Conduction lives in the window around µ₀

Today's question

Up to now everything was low bias. What does the electrostatic potential do at high bias, in the device at the heart of every chip: the nanotransistor?

Datta stresses that the field-less approach is for low bias. Here the field (electrostatics) enters.

Week 6Today's goals

  1. Use the point-channel model I = (1/q)∫G(E − U)[f₁ − f₂]dE to explain gate control.
  2. Explain saturation (µ₂ below the band edge) and why it is imperfect (α).
  3. Solve for the channel potential self-consistently: U = UL + U₀(N − N₀).
  4. Use the quantum capacitance CQ = q²D₀ in series with CE; explain 60 mV/decade.
  5. See how electrostatic asymmetry alone makes a rectifier.

Physics refresherRefresher: the MOS capacitor

  • Electron charge −q: a positive voltage lowers its energy, U = −qV.
  • Gate / oxide / channel = parallel-plate capacitor, CE = εA/tox.
  • One extra electron raises the channel energy by U₀ = q²/CE (charging energy).
  • Capacitors in series: 1/C = 1/C₁ + 1/C₂, the smaller one wins.

Datta Sec. 7.1How a gate controls the current

I = (1/q)∫dE G(E − U)[f₁(E) − f₂(E)]Eq. 7.1 · point-channel model
  • The FET is a voltage-controlled resistor: no gate current, VG sets the channel potential.
  • Positive VG: U = −qVG slides G(E) down into the window (Fig. 7.3).
  • n-type: more current. p-type (Fig. 6.2): less. That is CMOS.

Datta Sec. 7.2Why the current saturates, and why not perfectly

Isat = (1/q)∫dE G(E − U) f₁(E)Eq. 7.2 · µ₂ below the band edge, f₂ = 0
UL = α(−qVD) + β(−qVG)Eq. 7.3 · the drain also pulls the band
Ideal transistor: α → 0 (current set by VG only). That needs an oxide only a few atoms thick, controlled to atomic precision in a billion transistors.

InteractiveExplore: the nanotransistor

Nanotransistor explorer: the point-channel model  (Datta Sec. 7.1–7.4, Eqs. 7.1–7.9)

A 2D channel (m = 0.2 m₀, g = 2, W = L = 1 µm) between a source (μ₁ = 0) and a drain (μ₂ = −qVD). The gate lowers the band edge, the drain lowers it a little (α), and extra or missing electrons in the channel raise or lower it (charging, U₀). The potential U is found self-consistently (Fig. 7.7) and the current from I = (1/q)∫G(E)[f₁(E+U) − f₂(E+U)]dE (Eq. 7.7).

Current I (per µm width)–
Low-bias conductance dI/dVD–
Channel potential U (self-consistent)–
Electrons N / N₀–

Try this

  1. Raise VG: the band edge drops below µ₁ and the current grows.
  2. α = 0, no charging: flat saturation, N/N₀ ≈ 0.5.
  3. Set α = 0.2: the saturated current keeps rising.
  4. Press Fig. 7.9 setting: charging makes Isat ≈ 2.7×, low-bias slope unchanged.
  5. Press Fig. 7.11 setting, then α = 0.5: rectifier versus symmetric.

Scroll inside the panel for all controls. Swipe or use the arrow buttons outside it to change slide.

Point out the self-consistent U in the stats box and how N/N0 moves.

Datta Sec. 7.3Role of charging: a self-consistent loop

U = UL + U₀(N − N₀)(A) Eq. 7.4
N₀ = ∫D(E − U)f₀,   N = ∫D(E − U)(f₁ + f₂)/2(B1, B2) Eqs. 7.5–7.6
I = (1/q)∫G(E)[f₁(E + U) − f₂(E + U)]dE(C) Eq. 7.7

Under bias the drain empties what the source fills: fewer electrons, the channel turns positive, its states drop.

Datta Sec. 7.3Datta's Fig. 7.9: charging raises the saturation current

0.43 mAIsat, U₀ = 0 (W = 1 µm)
× 2.80U₀ very large
× 2.38U₀ = q²/CE, tox = 2 nm
12.5 mSlow-bias slope: same for all
2D: Isat ∝ (µ₁ − Ec)3/2. Keeping N = N₀ with half-filled states doubles µ₁ − Ec: 23/2 ≈ 2.8.
Parameters: m = 0.2 m0, g = 2, W = L = 1 µm, kT = 5 meV, mu0 − Ec = 50 meV, alpha = 0. All numbers from the Week 6 notebook.

Datta Sec. 7.3.1Quantum capacitance

C = q dN/dVG = CQ × dU/d(−qVG)Eq. 7.11
CQ = q²∫D(−∂f₀/∂E)dE = q²D₀Eq. 7.12
dU/d(−qVG) = 1/(1 + U₀D₀),  U₀D₀ = CQ/CEEqs. 7.13–7.14
CE and CQ in series: the channel itself resists being filled, in proportion to how few states it has.

Datta Sec. 7.3.1The 60 mV per decade rule

  • Below threshold µ is outside the band: f₀ ≈ e−(E−µ)/kT, so N ∝ e−U/kT.
  • Few electrons, D₀ ≈ 0: the band follows the gate one-for-one.
  • 10× more electrons needs ΔU = kT ln10 ≈ 60 meV, i.e. at least 60 mV of gate voltage.
This is why transistors cannot simply be run at lower voltages: a fundamental limit at room temperature for this way of switching.

InteractiveExplore: quantum capacitance

Quantum capacitance and the 60 mV per decade rule  (Datta Sec. 7.3.1, Eqs. 7.10–7.14)

Equilibrium (no drain bias). The gate tries to pull the 2D band edge down by qVG; the electrons that pour in charge the channel and push it back up. Below threshold almost nothing pushes back, so n grows 10× for every kT·ln10 ≈ 60 mV. Above threshold the oxide capacitance CE and the quantum capacitance CQ = q²D₀ act in series.

Electron density n–
CE = ε/tox · CQ here–
Gate efficiency dU/d(−qVG)–
Subthreshold slope–

Try this

  1. Below threshold: read the subthreshold slope (59.5 mV/dec at 300 K). Change T.
  2. Above threshold: the gate efficiency falls to 1/(1 + CQ/CE) ≈ 0.12.
  3. Thin the oxide to 0.5 nm: efficiency rises, more charge per volt.
  4. Light mass (0.03 m₀): CQ ≈ CE, the "quantum capacitance limit".

Scroll inside the panel for all controls. Swipe or use the arrow buttons outside it to change slide.

Efficiency + C/C_E = 1: what the band does not move, the charge makes up.

ApplicationQuantum capacitance in numbers

Datta's channel: 2D, m = 0.2 m₀, g = 2, ε = 4ε₀. CQ = q²gm/(2πħ²) = 13.4 µF/cm².

toxCE (µF/cm²)CQ/CEgate efficiencyseries C (µF/cm²)
1 nm3.543.780.212.80
2 nm1.777.560.121.56
5 nm0.7118.90.050.67
For silicon-like channels CE limits the charge. For light-mass channels (III–V, nanotubes) CQ becomes comparable and limits it instead.

Datta Sec. 7.4An electrostatic rectifier

  • A perfectly symmetric channel, µ₀ = Ec, no charging.
  • Standard FET: gate fixed to the source, α = 0: I(+V) ≠ −I(−V).
  • Floating gate: halfway between source and drain, α = 0.5: symmetric, "ohmic".
+0.15 / −1.14 mA(a) at ±0.1 V
±0.53 mA(b) at ±0.1 V

Same slope at V = 0 (4.8 mS): low bias never sees electrostatics.

Datta Figs. 7.10–7.11. The printed MATLAB code for this figure counts g twice; our notebook counts it once.

Datta Sec. 7.5Beyond a point: the extended channel

  • A field makes U(z) slope down to the drain: at a given E the drain end has more modes (Figs. 7.12–7.13).
  • Ballistic: the narrowest point limits G. Diffusive: the extra modes help.
dI/dz = 0,   I/A = −(σ₀/q) dµ/dzEqs. 7.16–7.17 · drift–diffusion, with Poisson (7.19)

Next week: this diffusion equation also describes ballistic channels, once its boundary conditions include RB.

CheckConcept check

One minute with a neighbour, then click to reveal.

1. Why does the current saturate once µ₂ is below Ec? (click)
f₂ = 0 wherever G ≠ 0: lowering µ₂ further changes nothing (Eq. 7.2).
2. Why is the low-bias conductance independent of charging and α? (click)
At low bias the current depends on G(E) near µ₀ (equilibrium); U changes only at second order.
3. Why ≈ 2.8× more saturation current with strong charging? (click)
Half-filled states must hold N₀: µ₁ − Ec doubles, and I ∝ (µ₁ − Ec)3/2 in 2D.
4. Why not faster than 60 mV/decade at 300 K? (click)
Below threshold n ∝ eqVG/kT at best: one decade per kT ln10.

Wrap-upFixed session summary

Take-home

  • Gate slides G(E); current needs states in the window
  • Saturation: µ₂ below Ec; imperfect via α and charging
  • U = UL + U₀(N − N₀), solved self-consistently
  • CQ = q²D₀ in series with CE; 60 mV/decade

Next: circular session C3

Refresher clinic → lab: DOS from 3D to 2D, counting modes, a self-consistent nanotransistor → problems → two-minute explanations. Open week06_nanotransistor_C3.ipynb (Part 2).

PART 2

Circular session C3

Covers Weeks 5–6 · about 85 minutes

A · 15 min
Refresher clinic
B · 55 min
Lab: DOS, modes, nanotransistor
C · 20 min
Problem clinic
D · 10 min
Two-minute explanations
If time is short, skip lab B2 (mode counting); it repeats Week 5.

Circular session C3Block A · Refresher clinic

In pairs: one explains, one sketches. Swap after each item.

1 · Counting

Why are allowed momenta evenly spaced, but energies not?

2 · Shapes

Sketch D(E) and M(E) for 1D, 2D and 3D parabolic bands.

3 · Holes

What does "n" count in a p-type band, and why?

4 · Series

Two capacitors in series: which dominates? Relate to CE and CQ.

Circular session C3Block B1–B2 · Lab: from 3D to 2D, and counting modes

A film of thickness t: subbands En = n²h²/8mt², each a 2D band. Per volume:

D = Σn gm/(2πħ²t)·ϑ(E − En)→ g·4πm√(2mE)/h³ as t grows
  1. At what t does the staircase look smooth below 0.2 eV?
  2. Compare t with λ at 100 meV (8.7 nm).
  3. B2: count modes on a grid and compare with Eq. 6.19.
Thin films (a few nm) show clear 2D steps; at 30 nm the staircase hugs the 3D curve.

Circular session C3Block B3 · Lab: a nanotransistor with a real gate

Let the gate charge the channel too: U = −βqVG − αqVD + U₀N, U₀ = q²/CE, for tox = 1, 2, 5 nm.

Predict first: thicker oxide, what changes below and above threshold? (click)
Below threshold nothing: all give ≈ 60 mV/dec (no charge to push back). Above threshold less current: C = CECQ/(CE + CQ) falls with CE.
Why is the oxide kept thin compared with L? (click)
So that the gate, not the drain, controls the channel: small α, flat saturation.

Notebook results

  • Subthreshold slope at tox = 2 nm: 59.6 mV/dec
  • I at VG = 0.6 V, VD = 0.5 V: 1 nm ≈ 1.85 mA, 2 nm ≈ 0.93 mA, 5 nm ≈ 0.36 mA

Circular session C3Block C · Problem clinic

P1. Datta's channel (2D, m = 0.2 m₀, g = 2, 1 µm × 1 µm, tox = 2 nm, ε = 4ε₀): find D₀, U₀ and U₀D₀. (click)
D₀ ≈ 8.35×10⁵ eV⁻¹; CE = 1.77×10⁻¹⁴ F; U₀ = q²/CE ≈ 9.05 µeV; U₀D₀ ≈ 7.6.
P2. Below threshold at 300 K with gate efficiency 0.8: how much VG for 1000× more current? (click)
3 × 59.5 mV / 0.8 ≈ 223 mV.
P3. GaAs 2D gas (0.067 m₀) under 3 nm of ε = 10ε₀ oxide: CQ, CE, series C? (click)
CQ ≈ 4.5 µF/cm², CE ≈ 2.95 µF/cm², C ≈ 1.8 µF/cm²: the quantum capacitance matters.

Circular session C3Block D · Two-minute explanations

Press the button for a two-minute topic.

Rules

  • No equations: a sketch is allowed
  • The partner asks one "why?" question
  • Swap roles for the next card

Wrap-upNext week: what and where is the voltage drop?

Before next class

  • Finish the Week 6 notebook (both parts)
  • Work through the Week 6 study toolkit
  • Read Datta Part A, Ch. 8–9 (pp. 99–119)

Week 7 preview

A diffusion equation for ballistic transport, two electrochemical potentials µ⁺ and µ⁻, the Boltzmann equation, and the difference between the electrostatic and the electrochemical potential.

Prof. Mohammad Razaghi · University of Kurdistan · after S. Datta, Lessons from Nanoelectronics